1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and method for controlling clock latency according to reordering of burst data.
2. Description of the Related Art
Semiconductor memory devices generally support a burst mode data transfer. In the burst mode, data corresponding to the read command are synchronized with a clock signal and are continuously and consecutively output. The burst data may be a plurality of data corresponding to column addresses that correspond to the read command and have a predetermined number of different least significant bits.
The number of continuously output data, for example, may be 4 or 8. In other words, in the burst mode, when a column address is input, column addresses corresponding to the rest of the data, that is, 3 or 7 units of data are automatically generated. This leads to the advantage that each data unit, such as a bit or byte, does not need its own addressing. Instead, only the first unit of data may have an address and then following consecutive data units are assumed to have the following consecutive addresses. The burst data are output in a fixed order.
FIGS. 1A and 1B are timing diagrams of burst data output from a semiconductor memory device. Referring to FIGS. 1A and 1B, the burst data are output in the order of “D1”, “D2”, “D3”, and “D4”, and “D3”, “D4”, “D1”, and “D2”, respectively. The semiconductor memory device stored the data in a memory cell array in the output order of the burst data shown.
However, a user may require a different output order of burst data than that output from the memory device. In order words, the user may prefer to reorder the burst data to be different than the order that it is output from the memory device.
However, reordering the burst data increasing the access time of the memory device.